A personal view of APL by Iverson K.E.

By Iverson K.E.

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Some examples of real instruction definition patterns from the CRIS port: (define_insn "xorsi3" [(set (match_operand:SI 0 "register_operand" "=r") (xor:SI (match_operand:SI 1 "register_operand" "%0") (match_operand:SI 2 "register_operand" "r")))] "" "xor %2,%0" [(set_attr "slottable" "yes")]) This is a very simple example. It defines a standard-named pattern for the xor-instruction. The mode of the operands is the 32 bits of the register (SImode). It only works for registers, so all operands use the predicate register operand.

29 See page 57. 2. THE PORTING MECHANISMS 51 Instruction splitting Sometimes the performance of the code can be improved by splitting up complex instructions into smaller ones. This happens for architectures with instructions with delayed or prolonged execution; when another instruction with some restrictions can be executed during the otherwise wasted delay. To profitably split up a complex instruction, there has to be a pattern to split it up into a set of smaller instructions, and another instruction with a “delay”, where a part can fit, for the sake of data dependence and target-dependent constraints.

If the only effect of the instruction is to set condition codes, then the target is expressed as cc0, but normally the condition-code setting is not expressed in the pattern. The target has the same appearance as an operand, but can not be an operation. more setting-expressions Optionally more (set . . )-expressions. Note that they are considered to be executed in parallel, so the output of one can not be used as the input of another. pattern-condition An optional (default true) condition for when the pattern applies.

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