Chemistry in Microelectronics by Yannick Le Tiec

By Yannick Le Tiec

Microelectronics is a posh global the place many sciences have to collaborate to create nano-objects: we want services in electronics, microelectronics, physics, optics and mechanics additionally crossing into chemistry, electrochemistry, in addition to biology, biochemistry and medication. Chemistry is interested in many fields from fabrics, chemical substances, gases, drinks or salts, the fundamentals of reactions and equilibrium, to the optimized cleansing of surfaces and selective etching of particular layers. moreover, over fresh a long time, the dimensions of the transistors has been enormously decreased whereas the performance of circuits has elevated. This ebook comprises 5 chapters protecting the chemical substances and sequences utilized in processing, from cleansing to etching, the position and impression in their purity, in addition to the fabrics utilized in “Front finish Of the road” which corresponds to the guts and function of person transistors, then relocating directly to the “Back finish Of the road” that's with regards to the interconnection of all of the transistors. ultimately, the necessity for particular functionalization additionally calls for key wisdom on floor remedies and chemical administration to permit new applications.

Contents

1. Chemistry within the “Front finish of the road” (FEOL): Deposits, Gate Stacks, Epitaxy and Contacts, François Martin, Jean-Michel Hartmann, Véronique Carron and Yannick Le Tiec.
2. Chemistry in Interconnects, Vincent Jousseaume, Paul-Henri Haumesser, Carole Pernel, Jeffery Butterbaugh, Sylvain Maîtrejean and Didier Louis.
3. The Chemistry of rainy floor instruction: cleansing, Etching and Drying, Yannick Le Tiec and Martin Knotter.
4. The Use and administration of Chemical Fluids in Microelectronics, Christiane Gottschalk, Kevin Mclaughlin, Julie Cren, Catherine Peyne and Patrick Valenti.
5. floor Functionalization for Micro- and Nanosystems: program to Biosensors, Antoine Hoang, Gilles Marchand, Guillaume Nonglaton, Isabelle Texier-Nogues and Francoise Vinet.

About the Authors

Yannick Le Tiec is a technical specialist at CEA-Leti, Minatec when you consider that 2002. he's a CEA-Leti assignee at IBM, Albany (NY) to increase the complicated 14 nm CMOS node and the FDSOI expertise. He held diverse technical positions from the complex three hundred mm SOI CMOS pilot line to various assignments inside SOITEC for complicated wafer improvement and later inside INES to optimize sunlight telephone ramp-up and yield. He has been a part of the ITRS entrance finish technical operating staff at ITRS due to the fact that 2008.

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The polycide/polysilicon gate was directly patterned using photolithography and etching of a deposited polycide/polysilicon stack layer according to a quite simple integration scheme. MoSi2 was the first polycide to be used and was replaced by WSi2 from the 1980s onwards, due to its lower resistivity (about 70 µΩ⋅cm vs. approximately 100 µΩ⋅cm for MoSi2). However, the device miniaturization was accompanied by an increase in series resistance in the source and drain region, so a metallic silicide layer with low resistivity at both the gate and the source and drain zones was introduced.

24. 2. 1. Growth mechanisms The annealing steps 3 and 5 lead to solid state reactions that constitute the core of the silicidation process. This part will first give some general information about Ni/Si systems and silicide formation. For more details in this area, the reader should refer [DHE 86], to which the following paragraphs refer. The phase diagram of the Ni/Si system at thermal equilibrium is relatively complex as it is made up of 11 phases of which only six are stable at standard temperature [NAS 87].

The polymorphic transformation of the C49 phase into C54 is controlled by the nucleation of the grain boundaries and so becomes difficult when the dimensions of the silicide zones are reduced [GAM 98]. 25 µm nodes onwards, TiSi2 was replaced by cobalt silicide (CoSi2) that has a similar resistivity but with fewer nucleation problems. 5 nm of CoSi2 [MAE 95]) as well as its high formation temperature (above 800°C) make it incompatible with the presence of ultra-shallow junctions. 23. Schematic diagrams of half a MOS transistor showing the different contributors to the series resistance in the source and drain region a) a transistor with direct metallic contact on silicon; b) a transistor with silicided zones.

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