Clock Generators for SOC Processors: Circuits and by Amr Fahim

By Amr Fahim

This ebook examines the difficulty of layout of fully-integrated frequency synthesizers appropriate for system-on-a-chip (SOC) processors. This e-book takes a extra worldwide layout standpoint in together studying the layout area on the circuit point in addition to on the architectural point. The assurance of the publication is entire and contains precis chapters on circuit conception in addition to suggestions regulate conception appropriate to the operation of section locked loops (PLLs). at the circuit point, the dialogue contains low-voltage analog layout in deep submicron electronic CMOS tactics, results of provide noise, substrate noise, besides equipment noise. at the architectural point, the dialogue comprises PLL research utilizing continuous-time in addition to discrete-time types, linear and nonlinear results of PLL functionality, and certain research of locking habit.

The fabric then develops into precise circuit and architectural research of particular clock new release blocks. This contains circuits and architectures of PLLs with excessive strength offer noise immunity and electronic PLL architectures the place the loop filter out is digitized.

Methods of producing low-spurious sampling clocks for discrete-time analog blocks are then tested. This comprises sigma-delta fractional-N PLLs, Direct electronic Synthesis (DDS) concepts and non-conventional makes use of of PLLs. layout for attempt (DFT) matters as they come up in PLLs are then mentioned. This comprises tools of safely measuring jitter and built-in-self-test (BIST) recommendations for PLLs. ultimately, clocking concerns generally linked to system-on-a-chip (SOC) designs, corresponding to a number of clock area interfacing and partitioning, and actual clock section new release options utilizing delay-locked loops (DLLs) also are addressed. The booklet presents quite a few actual international purposes, in addition to useful rules-of-thumb for contemporary designers to exploit on the process, architectural, in addition to the circuit point. This ebook is easily suited to practitioners in addition to graduate point scholars who desire to study extra approximately time-domain research and layout of frequency synthesis techniques.

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Extra resources for Clock Generators for SOC Processors: Circuits and Architectures

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Find h(t), the inverse Laplace Transform of H(s) 3. To guarantee accuracy at fixed time intervals of period T, let h[n]=h(nT) 4. Find the Z-transform of h[n] Using the steps listed above, one can easily calculate the open loop and closed loop transfer functions of the PLL. Figure 2-13 below compares the continuous-time to the discrete-time frequency transfer functions of a second order PLL. As the figure reveals, the discrete-time response of the PLL shows a larger closed loop bandwidth than its continuous-time model.

32) time to settle to the correct value, where b is the number of bits used to coarse tune the VCO and Tref is the reference period. After this period, the regular analog PLL loop takes over and requires additional time to lock. Also, the final coarse tune setting may be off by 1 LSB. This means that a minimum overlap of two coarse tune settings is required in the VCO characteristic shown in Figure 3-16. Additional overlap is also necessary to 3. Low-Voltage Analog CMOS Design 43 cover temperature and process variation.

26 Chapter 2 [12] D. Hess, "Cycle Slipping in a First-Order Phase-Locked Loop," IEEE Transactions on Communication Technology, vol. Com-16, no. 2, pp. 255-260, April 1968. [13] W. E. , 1990. [14] M. Soyuer and R. Meyer, "Frequency Limitations of a Conventional Phase-Frequency Detector," IEEE 7. of Solid-State Circuits, vol. 25, no. 4, pp. 1019-1022, August 1990. 1 Introduction High-performance and highly integrated SoCs have been mainly fueled by growing demand for high performance and equally growing demand for low cost.

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